Generally a DRAM comprises a memory cell having an access transistor and a storage capacitor, wherein the word line and the capacitor are connected with a gate and a source of the transistor respectively, and a drain of the transistor is connected to the bit line. Information is stored in the memory cell by charging a voltage of the bit line to the capacitor by turning on the transistor. After an active cycle (read or write cycle), a word line voltage is reset to a ground voltage so as to turn off the access transistor and accordingly the charged voltage of the storage capacitor is maintained in a stand-by state.
In case of a density of memory of a DRAM being increased, width and length of a channel of the transistor are required to be reduced so as to minimize an area occupied by the transistors. Such a scale-down of design rule requires a design rule of sub-micron in manufacturing a DRAM of tens of mega-RAMs. Accordingly a using voltage should be lowered to an extent of a source voltage of about 3 volts in order to solve a problem of break down voltage of a drain of the transistor. Such a low voltage as well as a short channel of the transistor create a sub-threshold phenomenon, namely a current can flow through a drain-source of the transistor even if a gate-source voltage is lower than a threshold voltage. Therefore, there is occurred a problem that a voltage charged in the capacitor of the memory cell is discharged through the drain-source path of the access transistor even if the access transistor is turned off in the stand-by state and a refresh operation should be performed within a quicker time. A prior art for solving the above mentioned problems is disclosed in the U.S. Pat. No. 4,610,003.
With reference to FIG. 1 illustrating the prior art, a word line drive circuit comprises a storage capacitor 22, a memory cell 20 having an access transistor 24 of which a source and a drain are connected between the capacitor and a bit line 26, a word line 28 connected to a gate of the transistor 24, a drive circuit 10 for driving the word line 28 by a given voltage through a switching transistor 14 in a read, write or refresh operation, a control circuit 12 for turning on the switching transistor 14 in response to an output of the drive circuit 10 in driving the word line, an oscillator 34 for generating a pulse of square wave having a given width of pulse, a charge pump circuit 30 for charging a capacitor 32 by generating a negative voltage in response to a pulse of the oscillator, and a transistor 18 of which a drain-source path is connected between an output end of the charge pump circuit 30 and the word line 28 and a gate is connected to an output of an inverter 16 for inverting an output of the control circuit 12. All transistors illustrated in FIG. 1 are the N channel MOS IG FET's, and a source supply voltage Vc is 5 volts.
FIG. 2 shows a voltage supplied from the word line 28 to the transistor 24 of the memory cell 20 as illustrated in FIG. 1. When the drive circuit 10 is activated by an address signal designating the memory cell 20, the drive circuit is converted from a ground voltage state to a source voltage Vc. By the source voltage Vc, the control circuit 12 is activated and generates a voltage of more than Vc+Vth so as to turn on the switching transistor 14. By the voltage of more than Vc+Vth, an output voltage Vc of the drive circuit 10 is supplied to the word line 28, which turns on the access transistor 24 by being charged with a source voltage Vc. On one hand, the transistor 18 is turned off by an output of the control circuit 12 and the inverter 16. The storage capacitor 22 is connected to the bit line through the transistor 24 and an information voltage stored in the capacitor 22 is discharged into the bit line 26. In other words, the bit line 26 is charged with the information voltage. When the drive circuit 10 is turned off, a ground voltage is transmitted. Accordingly the control circuit 12 generates a ground voltage state, the switching transistor 14 is turned off and the transistor 18 is turned on. Consequently a negative voltage of -3 volts charged in the capacitor 32 is transmitted to the word line 28 through the transistor 18. As a result the access transistor 24 is blocked deeply so as to prevent a sub-threshold current. When the storage capacitor 22 is charged with the source voltage Vc of 5 volts and the word line 28 is charged with the negative voltage, the charged voltage of the storage capacitor 22 is prevented from leaking because a gate-source voltage of the access transistor 24 is much lower than its threshold voltage.
In a conventional art, however, there is occurred a problem that the charge pump circuit is loaded greatly because the word line voltage is increased suddenly from a non-selection voltage of -3 volts to a selection voltage of 5 volts in selecting a word line and reduced suddenly from a boosted voltage of 5 volts to a negative voltage of -3 volts in a read/write operation (memory cycle). Furthermore, such a sudden voltage change of the word line may cause a damage on a memory device by breaking a thin oxide insulated film of a gate of transistors connected with word lines.
Such a sudden voltage change may be transferred to an adjacent line through a parasitic capacitance such that a false operation of a memory device may be brought about. Also in an LSI DRAM, a bump phenomenon of a source voltage of an oscillator is occurred due to a sudden increase of load of a charge pump circuit such that an false operation of a memory device is caused.